1. Field of the Invention
This invention relates to a gallium arsenide MESFET memory and, more specifically, to a gallium arsenide MESFET memory which utilizes enhancement mode (e-mode) transistors in the memory cells and depletion mode (d-mode) transistors in the driver circuits.
2. Brief Description of the Prior Art
Prior art gallium arsenide memory circuits, such as, for example, one reported in Paper No. 4 of the Gallium Arsenide IC Symposium of 1981, used a quasi-normally-off gallium arsenide FET where the threshold voltage, V.sub.t, for the switching FETs is chosen to be approximately zero. By using appropriate biasing schemes, such circuits using what is termed low pinch-off FET logic were operated with wider threshold variations (i.e., V.sub.t approximately .+-.0.15 volts for V.sub.t approximately zero volts) with a corresponding increase in circuit power dissipation. In another prior art publication entitled Gallium Arsenide Memory Technology Development Technical Report, by W. V. McLevige, et al., AFWAL-TR-81-1290, Mar. 19, 1982, all switching functions were designed with small e-mode MESFETs. While the e-mode memory cells have performed well, the limited current carrying capacity of the e-mode MESFET tends to require large e-mode MESFETs in the peripheral driving circuits (i.e., with large device width). This large device width can result in a decrease in circuit speed as well as an increase in circuit power dissipation. The desire in the art is to provide a gallium arsenide memory wherein power dissipation is minimized and wherein the chip area occupied by the components is also minimized.